The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a source/drain region having a reduced area and a reduced parasitic capacitance and parasitic resistance. The present invention also relates to a method for producing the same, and an information processing apparatus.
Recently, the integration level of a semiconductor device is becoming higher and higher. There is an increasing demand for even smaller elements. In the case of a typical insulated gate type field effect transistor, as the size thereof is made smaller, the following problems become more significant: variations in threshold voltage due to variations in gate length caused upon manufacturing; an increase in off-leakage current due to degradation of sub-threshold characteristics; degradation of transistor characteristics due to a short channel effect such as punch-through.
There are known methods for solving the above-described problems which become evident due to size reduction. In one of the known methods, the junction of the source/drain region adjacent to the channel region of a transistor is formed at a shallow level. The term xe2x80x9csource/drain regionxe2x80x9d means a source or drain region, or source and drain regions. To form the shallow junction, the source/drain regions are provided on opposite sides of a gate electrode via a gate electrode side wall insulating film, and are each accumulated to a level higher than a channel region (i.e., a surface of a semiconductor substrate under the gate electrode where the surface will be reversed by electric field of the gate electrode). Such source/drain regions are referred to as accumulated diffusion layer.
FIGS. 43(a) to (c) are diagrams showing the steps of producing a conventional accumulated diffusion layer. Hereinafter, the steps of producing a conventional accumulated diffusion layer will be described with reference to FIGS. 43(a) to (c).
As shown in FIG. 43(a), a surface of a semiconductor wafer 1001 includes an isolation region 1002 and an active region 1003. A silicon oxide film 1042 is provided in the isolation region 1002. In the active region 1003, the silicon substrate 1001 (semiconductor wafer) is exposed.
In the production steps of a conventional accumulated diffusion layer, initially, a gate electrode 1005 is formed on the active region 1003 via a gate insulating film 1004. The top and the side walls of the gate electrode 1005 are covered with an insulating film 1006.
Thereafter, as shown in FIG. 43(b), a silicon film 1007 is grown by a selective epitaxial growth method only on an exposed region (active region 1003) of the silicon substrate 1001. The silicon film 1007 will become a semiconductor accumulated diffusion layer and serve as a source/drain region. The selective epitaxial growth method is disclosed in Japanese Laid-open Publication No. 61-196577, for example.
Thereafter, as shown in FIG. 43(c), an interlayer insulating film 1008 is provided. A conductor 1010 formed on the interlayer insulating film 1008 is connected to the silicon film 1007 (source/drain region) via a contact conductor 1009. The silicon film 1007 is made of epitaxial silicon, polycrystalline silicon, or the like.
In the conventional technique described with reference to FIGS. 43(a) to (c), after the silicon film 1007 has been provided to a level higher than the channel region, impurity ions are implanted into the silicon film 1007 in the vicinity of the channel region to form a source/drain region.
The impurity ions are implanted into the silicon film 1007 which has been accumulated to a level higher than the channel region, so that the junction depth of the impurity diffused layer of the source/drain region can be made shallow. Thereby, the short channel effect can be effectively prevented.
As shown in FIG. 43(c), a contact hole for the contact conductor 1009 is provided in the silicon film 1007 (source/drain region) which is positioned between the gate electrode 1005 and the isolation region 1002. A length Ld along the gate length direction (perpendicular to the longitudinal direction of the gate electrode) of the source/drain regions 1007 cannot be less than (an alignment margin between the gate electrode and the contact)+(a width along the gate length direction of the contact hole)+(an alignment margin between the contact and the source/drain region).
Therefore, there is a problem with the semiconductor device of FIG. 43(c) in that it is difficult to reduce the planer size of the source/drain region.
Japanese Laid-open publication No. 10-335660 discloses a method which provides a solution to the above-described problem.
FIG. 44 is a diagram showing an insulating gate type field effect transistor disclosed in Japanese Laid-open publication No. 10-335660.
In the insulating gate type field effect transistor, isolation insulating regions 2002 are disposed below a gate electrode 2005 in a semiconductor substrate 2001. A region between the isolation insulating regions 2002 is called a device region. A distance between a side of the gate electrode 2005 and a point of one of the isolation insulating regions 2002 contacting a portion of the device region in which two diffusion layers 2012 and 2013 are provided is less than or equal to the height of the gate electrode 2005. A distance between an edge at the gate electrode side and an edge at the isolation insulating region side of the upper diffusion layer 2012 is greater than or equal to the height of the gate electrode 2005. The edge at the isolation insulating region side of the upper diffusion layer 2012 is disposed on the isolation insulating region 2002.
FIGS. 45(a) to (e) are diagrams showing a production process of the insulating gate type field effect transistor disclosed in Japanese Laid-open publication No. 10-335660.
FIG. 45(a) shows a structure resulting from the following steps in the production process of the insulating gate type field effect transistor provided in a semiconductor device. An isolation insulating region 3002 is formed in a first conductivity semiconductor substrate 3001, providing a device region surrounded by the region 3002. In this case, a distance between a side of a gate electrode 3005 which will be provided in the device region and a point of the isolation insulating region 3002 contacting a portion of the device region in which two diffusion layers will be provided is less than or equal to the height of the gate electrode 3005. A well region 3014 is formed in the device region. A gate insulating film 3003 is formed on the device region. The gate electrode 3005 is formed on the gate insulating film 3003. Second conductivity impurities are implanted into the device region by an ion implantation method using the gate electrode 3005 as a mask, the second conductivity being different from the first conductivity. Thereby, a shallow diffusion layer 3013 (lower diffusion layer) is provided in the vicinity of a surface of the device region.
FIG. 45(b) shows a structure resulting from the following steps. An oxide film is deposited on the gate insulating film 3003 by a chemical vapor growth method. Unwanted portions of the oxide film and the gate insulating film 3003 are removed by anisotropic etching. An insulating gate side wall 3007 is formed at a side of the gate electrode 3005 in a self alignment way.
FIG. 45(a) shows a structure resulting from the following steps. A polycrystalline silicon film 3015 is deposited to the same height as that of the gate electrode 3005.
FIG. 45(d) shows a structure resulting from the following steps. An upper diffusion layer 3012 is provided. In this case, a distance between an edge at the gate electrode side and an edge at the isolation insulating region side of the upper diffusion layer 3012 is greater than or equal to the height of the gate electrode 3005. The edge at the isolation insulating region side of the upper diffusion layer 3012 is disposed on the isolation insulating region 3002.
FIG. 45(e) shows a structure resulting from the following steps. An insulating film 3009 is deposited and provided as an interlayer film. A contact hole is formed in the interlayer film. An electrode metal 3010 is provided in the contact hole so that at least a portion of an end of the electrode metal 3010 is connected to the upper diffusion layer 3012.
In the technique disclosed in Japanese Laid-open Publication No. 10-335660, the distance between a side of the gate electrode 2005 and a point of the isolation insulating region 2002 contacting a portion of the device region in which two diffusion layers 2012 and 2013 (FIG. 44) are provided is less than or equal to the height of the gate electrode 2005. The minimum of such a distance is determined by an alignment margin between the isolation region and the gate electrode, and the thickness of the gate electrode side wall insulating film. The height of the gate electrode is designed to be greater than or equal to the distance.
The distance between a side of the gate electrode 2005 and a point of the isolation insulating region 2002 contacting a portion of the device region, in which two diffusion layers 2012 and 2013 are provided, greatly depends on the processing accuracy of an apparatus used for manufacture. In an embodiment of the conventional technique disclosed in Japanese Laid-open Publication No. 10-335660, the gate electrode is processed into a width of 100 nm. In general, the width of the gate electrode (gate length) is designed to be equal to the minimum processable size. Accordingly, it is believed that a semiconductor device according to the embodiment of this conventional technique is produced using a apparatus performance of 100 nm rule. A typical photolithography apparatus has an alignment accuracy which is one third of the minimum processable size. Therefore, an alignment margin for the isolation region requires 33 nm or more. Further, in the embodiment of this conventional technique, the thickness of the gate electrode side wall insulating film is 50 nm. A margin having a total of 83 nm is required. The distance between a side of the gate electrode 2005 and a point of the isolation insulating region 2002 contacting a portion of the device region in which two diffusion layers 2012 and 2013 are provided is about 75 nm in a state in which the alignment of the gate electrode to the isolation insulating region is perfect, as described in the embodiment of the conventional technique. However, when the alignment includes a deviation of 33 nm, the distance falls within the range of 42 nm to 108 nm. In view of this, a margin of alignment is secured in the specific values in the embodiment of this conventional technique. It is thus believed that 350 nm and 150 nm values are valid values for the distance between the isolation regions and the height of the gate, respectively.
As described in Japanese Laid-open Publication No. 10-335660, there is a known method in which introduction of impurities into the gate electrode made of a polycrystalline silicon film, and introduction of impurities into the source/drain region by ion implantation are simultaneously conducted for the purpose of simplifying the process. When a voltage is applied to the gate electrode, if the difference in work function between the gate electrode and an electrode (in this case, the semiconductor substrate) opposing the gate electrode via the gate oxide film causes the energy band to be bent in a region where the gate electrode contacts the gate oxide film (i.e., depletion occurs in the gate electrode), the gate insulating film capacitance is connected in series to the gate electrode depletion layer capacitance. In this case, the voltage applied to the gate electrode is divided and applied to the gate insulating film capacitance and the gate electrode depletion layer capacitance. Thus, the performance of the transistor is reduced. To avoid the depletion in the gate electrode, impurities need to be introduced into the gate electrode along the height direction thereof so as to obtain a high concentration of at least 1xc3x971020/cm3 or more. Therefore, a sufficient thermal processing is generally required after implantation of the impurity ions having such a high concentration. In the process of the thermal processing, the impurities implanted into the source/drain region are diffused, as is the impurities implanted into the gate electrode.
When the gate height is great, if the impurities are implanted in a high concentration into the gate electrode so as not to cause depletion, the impurities implanted into the source/drain region are diffused into the semiconductor substrate in the process of the thermal processing, thereby forming an adversely deep diffusion layer having a high concentration of the impurities. Such a problem is not described in Japanese Laid-open Publication No. 10-335660.
As described in FIG. 44, Japanese Laid-open Publication No. 10-335660 also discloses a technique in which a vertical step portion is provided in a region where the source/drain region (upper diffusion layer 2012) contacts the isolation insulating region 2002. The contact hole is provided on the step. When etching is used to provide the contact hole, the selectivity of the interlayer insulating film to the etching stop film (etching selectivity ratio) is lowered. When the etching selectivity ratio is lowered in the formation of the contact hole in the interlayer insulating film, the polycrystalline silicon film which will be the source/drain region is dug or the isolation region is dug. Thereby, a contact resistance between the electrode metal 2010 and the source/drain region (upper diffusion layer 2012) are adversely increased.
Such a problem is not described in Japanese Laid-open Publication No. 10-335660.
The present invention is provided to solve the above-described problems. An objective of the present invention is to provide a semiconductor device having a small planer size of a source/drain region, and a production method thereof. Further, another object of the present invention is to provide a semiconductor device in which a high integration level is obtained by reducing a margin between each gate electrode. Furthermore, a yet still another object of the present invention is to provide an information processing apparatus having a small level of power consumption.
A semiconductor device according to the present invention comprises: a semiconductor substrate comprising an isolation region and an active region; a gate electrode provided on the active region via a gate insulating film, at least part of a side of the gate being covered with a gate electrode side wall insulating film; and a source region and a drain region provided on respective sides of the gate electrode via the gate electrode side wall insulating film. The source region includes a first source region provided above a first surface where the active region contacts with the gate insulating film, and a second source region provided below the first surface. The drain region includes a first drain region provided above the first surface, and a second drain region provided below the first surface. At least one of the source and drain regions has a second surface for contacting a contact conductor, the second surface being tilted with respect to the first surface. At least part of the first source region is provided on the isolation region. At least part of the first drain region is provided on the isolation region. An angle between the second surface and a surface of the isolation region is 80 degrees or less. Thereby, the above-described objective is achieved.
In a cross-sectional view along a gate length direction, the second surface may be in a convex shape, and a height of the second surface from the first surface may be monotonically decreased in a direction leaving from the gate electrode.
In a cross-sectional view along a gate length direction, the second surface may be in a concave shape, and a height of the second surface from the first surface may be monotonically decreased in a direction leaving the gate electrode.
The second surface may be rough.
In a cross-sectional view along a gate length direction: a depth of a junction between the second source region and the semiconductor substrate from the first surface may be monotonically increased in a direction leaving the gate electrode; and a depth of a junction between the second drain region and the semiconductor substrate from the first surface may be monotonically increased in a direction leaving the gate electrode.
In a cross-sectional view along a gate length direction, at least one of a width of the first source region in the gate length direction and a width of the first drain region in the gate length direction may be greater than or equal to the sum of a width of the gate electrode side wall insulating film in the gate length direction and a width of the gate electrode in the gate length direction.
The surface of the isolation region may be above the first surface.
In a cross-sectional view along a gate length direction, a shortest distance between an edge of the gate electrode side wall insulating film and the isolation region may be smaller than a width of the gate electrode in the gate length direction.
In a cross-sectional view along a gate length direction, a shortest distance between an edge of the gate electrode and the isolation region may be greater than a height of the gate electrode.
In a cross-sectional view along a gate length direction, a shortest distance between an edge of the gate electrode side wall insulating film and the isolation region may be smaller than a height of the gate electrode side wall insulating film.
In a cross-sectional view along a gate length direction, a distance between the first surface and an upper surface of the gate electrode is smaller than at least one of a distance between the first surface and a point where a surface of the first source region contacts the gate electrode side wall insulating film and a distance between the first surface and a point where a surface of the first drain region contacts the gate electrode side wall insulating film.
In a cross-sectional view along a gate length direction: a depth of a junction between the second source region and the semiconductor substrate from the first surface may be 0.8 to 2 times a width of the gate electrode side wall insulating film in the gate length direction; and a depth of a junction between the second drain region and the semiconductor substrate from the first surface may be 0.8 to 2 times a width of the gate electrode side wall insulating film in the gate length direction.
The first drain region may include an impurity for determining a conductivity of the first drain region, an impurity concentration of at least part of the first drain region being more than 1xc3x971020/cm3. The second drain region may include an impurity for determining a conductivity of the second drain region, an impurity concentration of at least part of the second drain region being more than 1xc3x971020/cm3. The first source region may include an impurity for determining a conductivity of the first source region, an impurity concentration of at least part of the first source region being more than 1xc3x971020/cm3. The second source region may include an impurity for determining a conductivity of the second source region, an impurity concentration of at least part of the second source region being more than 1xc3x971020/cm3.
At least part of the first source region may be made of a polycrystalline silicon film. At least part of the first drain region is made of a polycrystalline silicon film.
At least part of the first source region may be made of a silicon-germanium film. At least part of the first drain region may be made of a silicon-germanium film.
In a cross-sectional view along a gate length direction, a grain size of the polycrystalline silicon film may be smaller than a shortest distance between an edge of the gate electrode side wall insulating film and the isolation region.
In a cross-sectional view along a gate length direction, a grain size of the silicon-germanium film may be smaller than a shortest distance between an edge of the gate electrode side wall insulating film and the isolation region.
At least one of the second source region and the second drain region may be produced by the steps of: implanting an impurity into a layer to be the first source region or the first drain region, the impurity causing the layer to have conductivity opposite to the conductivity of the active region; and diffusing the impurity from the layer to be the first source region or the first drain region, into the active region.
A diffusion coefficient of at least one of the layer to be the first source region and the layer to be the first drain region may be greater than a diffusion coefficient of the semiconductor substrate.
Another semiconductor device according to the present invention comprises a semiconductor substrate and a plurality of field effect transistors provided on the semiconductor substrate. Each of the plurality of field effect transistors includes: a gate electrode provided on the semiconductor substrate; a gate electrode side wall insulating film provided at a side of the gate electrode; and a conductive film to be a source region or a drain region, provided at a side of the gate electrode via the gate electrode side wall insulating film; the gate electrode of each of the plurality of field effect transistor is produced by the step of dividing a first non-insulating film into a plurality of regions; and the conductive film of each of the plurality of field effect transistor is produced by the step of dividing a second non-insulating film into a plurality of regions. Thereby, the above-described objective is achieved.
Another semiconductor device according to the present invention comprises a semiconductor substrate and a plurality of field effect transistors provided on the semiconductor substrate. Each of the plurality of field effect transistors includes: a well region provided on the semiconductor substrate; a gate electrode provided on the well region via a gate insulating film; a gate electrode side wall insulating film provided at a side of the gate electrode; and a conductive film to be a source region or a drain region, provided at a side of the gate electrode via the gate electrode side wall insulating film. The gate electrode of each of the plurality of field effect transistor is produced by the step of dividing a first non-insulating film into a plurality of regions. The conductive film of each of the plurality of field effect transistor is produced by the step of dividing a second non-insulating film into a plurality of regions. Thereby, the above-described objective is achieved.
At least one of the plurality of field effect transistors may further comprise a terminal provided on the well region for setting the potential of the well region. The semiconductor device may further comprise a voltage generation circuit connected to the terminal; and the voltage generator circuit changes the potential of the well region depending on whether the at least one of the plurality of field effect transistors is in an active state or a standby state.
Another semiconductor device according to the present invention comprises a semiconductor substrate and a plurality of field effect transistors provided on the semiconductor substrate. Each of the plurality of field effect transistors includes: an isolation region; a deep well region of a first conductivity; a shallow well region of a second conductivity provided in the deep well region, the second conductivity being opposite to the first conductivity; a gate electrode provided on the shallow well region via a gate insulating film; a gate electrode side wall insulating film provided at a side of the gate electrode; and a conductive film to be a source region or a drain region, provided at a side of the gate electrode via the gate electrode side wall insulating film. The gate electrode of each of the plurality of field effect transistor is produced by the step of dividing a first non-insulating film into a plurality of regions. The conductive film of each of the plurality of field effect transistor is produced by the step of dividing a second non-insulating film into a plurality of regions. At least one of the plurality of field effect transistors is a dynamic threshold transistor in which the shallow well region of the second conductivity is electrically connected to the gate electrode. The shallow well region of the dynamic threshold transistor is electrically isolated from the shallow well regions of the other field effect transistors via the isolation region and the deep well region. Thereby, the above-described objective is achieved.
A method for producing a semiconductor device according to the present invention, comprises the steps of: forming a first non-insulating film pattern by patterning a first non-insulating film to a desired pattern on a semiconductor substrate; forming a side wall insulting film at a side of the first non-insulting film pattern; depositing a second non-insulating film; forming a side wall consisting of the second non-insulating film at a side of the first non-insulting film via the side wall insulating film by an isotropic etching until the second non-insulating film is removed from an upper portion of the first non-insulating film pattern; and forming a layer to be a gate electrode, a layer to be a source region, and a layer to be a drain region by patterning the first non-insulating film pattern and the side wall by selectively etching with respect to the side wall insulating film.
The method may further comprise the step of simultaneously implanting a donor or an acceptor into the layer to be a gate electrode, the layer to be a source region, and the layer to be a drain region.
The selective etching with respect to the side wall insulating film may be an anisotropic etching including an isotropic component.
In the selective etching with respect to the side wall insulating film, an isotropic etching maybe conducted after an anisotropic etching.
A diffusion coefficient of at least one of the layer to be a source region and the layer to be a drain region may be greater than a diffusion coefficient of the semiconductor substrate.
Another method for producing a semiconductor device according to the present invention, comprises the steps of: attaching a first insulating film on a first non-insulating film provided on a semiconductor substrate; forming a first non-insulating film pattern and a first insulating film pattern by patterning a first non-insulating film and the first insulating film to a desired pattern; forming a side wall insulting film at a side of the first insulting film pattern; depositing a second non-insulating film; forming a side wall consisting of the second non-insulating film at the sides of the first non-insulting film pattern and the first insulating film pattern by an isotropic etching until the second non-insulating film is removed from an upper portion of the first non-insulating film pattern: exposing a surface of the first non-insulating film pattern by selectively removing the first insulting film pattern: forming a layer to be a gate electrode, a layer to be a source region, and a layer to be a drain region by patterning the first non-insulating film pattern and the side wall by selectively etching with respect to the side wall insulating film.
The method may further comprise the step of simultaneously implanting a donor or an acceptor into the layer to be a gate electrode, the layer to be a source region, and the layer to be a drain region.
The selective etching with respect to the side wall insulating film may be an anisotropic etching including an isotropic component.
In the selective etching with respect to the side wall insulating film, an isotropic etching may be conducted after an anisotropic etching.
A diffusion coefficient of at least one of the layer to be a source region and the layer to be a drain region may be greater than a diffusion coefficient of the semiconductor substrate.
An information processing apparatus comprises a display device and an operation device for controlling the display device, the apparatus being able to be driven by a battery. The operation device comprises a circuit including the semiconductor device of the present invention. Thereby, the above-described objective is achieved.